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OSU SoC Design Flow Notes

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Welcome to the OSU SoC Design Flow Notes. This page will link you to some VLSI information pages and tutorials to create your own Cadence or Magic Librairies and have them verified. Have a nice visit...

New: Visit Chiptalk.org, post your questions, see what others are writing, check out industry headlines and much more! This website has more up to date tutorials as well.

1. Tutorials
   • Synopsys Design Compiler and Silicon Ensemble (html)
   • Cadence Build Gates and Encounter (html)
   • Step-by-Step Tutorial for Cadence Encounter (html)
   • Simulation-based Power Analysis in Encounter (html)
   • A sample example using Cadence PKS, Silicon Ensemble, Synopsys Primetime and Magic 6.5
     • 27-page Picture Tutorial (html) (pdf)
     • accu.v
     • accu_test.v
     • accu.cmd
   • A second example that adds IO Pads to the accu design
     • 35-page Picture Tutorial (html) (pdf)
     • accu.v
     • accu_test.v
     • accu.cmd
   • Cadence Tutorials (html)

2. Older tutorials
   • Magic Overview (html)
   • Magic Tutorial for a Simple CMOS Inverter (html)
   • IRSIM Tutorial (html)
   • Pplot Tutorial (html)
   • Gemini Tutorial (html)
   • Using the OSU cells with Magic and Sue (html)

3. Hints and Tips regarding Verilog and Synthesis. (mostly for OSU students, but may be useful)
4. The routing grid.
In case you want to add your own cells to our library, you will need to utilize our grid structure. Please read the following regarding the grid size.
5. Creating the abstracts.
Cadence's Abstract Generator
6. Environmental setup files for use with our Unix Solaris system. They are referred to in the tutorials below. They are useful for those interested in the setup. Please note that all of these scripts assume we utilize the C or Turbo C shell
   
   • Magic and SoC design flow
     
   • Cadence Design System tools
     
   • Synopsys tools